IC Packaging Engineer

Summary

At Apple, we believe our products begin with our people. By hiring a team with varied strengths, we drive creative thought. By giving that team everything they need, we drive innovation. By hiring incredible engineers, we drive precision. And through our collaborative process, we build memorable experiences for our customers. These elements come together to make Apple an amazing environment for motivated people to do the greatest work of their lives. You will become part of a hands-on development team that sets the standard in cultivating excellence, creativity and innovation. Will you help us design the next generation of revolutionary Apple products?

Description

We are looking for a senior level IC packaging engineer to develop exciting new products. Your role is to interface between internal product/device design, quality, supply chain, and the external suppliers to develop and deploy new packaging technologies. We are looking for individuals who are very innovative with a proven track record to bring packaging solution from concept to high-volume manufacturing.

Key Responsibilities

Explore and evaluate packaging technologies as our own packaging tool box. Define new package characteristics and specification based on unique module and system level performance, cost, and footprint. Work with leading foundry, assembly OSATs & equipment/material suppliers on the development of advanced wafer bumping, wafer level chip scale packaging, fcCSP and SiP integration from design, new material, new equipment selection and establish robust process of record. Perform initial proof of concept sample build, package and process qualification, reliability test, yield analysis and continuous improvement. Interface and coordinate with other cross functional teams to comply with product development & ramp schedule. Deliver packaging POR and qualification milestones on time. Collaborate with internal team on pathfinding and jointly define packaging roadmap based on long term product requirements. Work closely and manage suppliers’ development activities. At least 5~10% travel to domestic and international locations.

Minimum Qualifications

M.S or Ph.D. degree in mechanical engineering, physics, materials science or similar disciplines with a minimum of 5 years of experience in IC packaging. In-depth knowledge in wafer bumping, PM/RDL fan-in & fan-out & system-in-package integration, good understanding to module process such as Cu RDL, polymer passivation, advanced node wafer singulation and die level process. Good understanding to Chip on Wafer hybrid or fusion bonding technologies is a plus.

Preferred Qualifications

Knowledge in wafer level CSP, fcCSP, SiP and their corresponding applications in power management, baseband and RF. Good understanding to advanced silicon node BEOL and device physics or component/board level reliability testing. Proven track record to drive issue resolution with good understanding to root cause and physics, motivate and mobilize all levels within supplier to accomplish any given task. Able to perform independent research and development work with minimal supervision. Good written and verbal communication skills. Able to present ideas, design concepts, data and plan with high confidence at internal or external meetings.