ASIC Engineer, Design
Meta·Austin, Texas, United States | Sunnyvale, California, United States·posted 13d ago · last seen 23m agoTrack this application
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Recruiter screen, a technical screen (60-minute asynchronous challenge or paired live coding), a short culture-fit questionnaire, then a virtual onsite of about four rounds: fast-paced coding with multiple problems per round, system design scoped to level, a lighter behavioral, and an AI-enabled coding round assessing how you work with a coding assistant.
Read the full Meta interview process →Description
About
Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration.
Responsibilities
- Architecture exploration
- Micro-architecture development
- Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
- Collaboration with implementation team to close the design on timing and power
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
- RTL development using Verilog, System Verilog and HLS Experience in CPU, NOC, Memory and Peripheral Subsystems
- Experience with Synthesis, Timing Closure and Formal Verification Methodology
- Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
- Experience in data path development
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