ASIC Engineer, Design Verification

About

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing proficiency with increased capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains.

Responsibilities

• Develop functional tests based on verification test plan
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
• Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification criteria

Minimum Qualifications

• Currently has, or is in the process of obtaining a Bachelor's degree in Electronics Engineering, Computer Engineering, Computer Science, Very Large Scale Integration (VLSI), relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• Experience using constrained-random, coverage driven verification or C/C++ verification
• Experience in verifying a IP block using standard Design Verification (DV) based techniques
• Experience in Electronic Design Automation (EDA) tools and scripting (Python, Tool Command Language (TCL), Perl, Shell) used to build tools and flows for verification environments
• Understanding in at least one of the following areas: computer architecture, Central Processing Unit (CPU), Graphics Processing Unit (GPU), networking, interconnects, fabrics or similar designs Currently has, or is in the process of obtaining, a Master’s degree in Electronics Engineering, Computer Engineering, Computer Science or similar technical field
• Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools
• Experience in development of SystemVerilog/UVM based verification environments from scratch
• Experience in verification of any peripheral IPs like UART, SPI, I2C and exposure to protocols like APB, AXI
• Experience with revision control systems like Mercurial(Hg), Git or SVN
• Experience working in a CPU/GPU environment