Digital Design Engineer, SoC Chassis
Track this application
Get Started FreeMatch score against your CV
Get Started FreeTailor your resume to this job
Get Started FreeAbout interviewing at Meta
Recruiter screen, a technical screen (60-minute asynchronous challenge or paired live coding), a short culture-fit questionnaire, then a virtual onsite of about four rounds: fast-paced coding with multiple problems per round, system design scoped to level, a lighter behavioral, and an AI-enabled coding round assessing how you work with a coding assistant.
Read the full Meta interview process →Description
About
Meta is seeking design engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning and network acceleration. You will collaborate with researchers and engineers to design, implement, and optimize low-power hardware accelerators, state-of-the-art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.
Responsibilities
- Contribute to ASIC digital µArchitecture and design
- Assist in the performance/power analysis of the design and help meet power and performance targets
- Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
- Collaborate with adjacent teams such as Verification, Physical Design, and Design for Test
- Develop micro-architecture, RTL coding, and design verification for complex IPs
- Drive the IP/sub-system micro-architecture and RTL design in collaboration with DV and PD leads
Minimum Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
- 6+ years of experience as a hardware design engineer for production silicon shipped in volume
- Experience in digital design µArchitecture, RTL coding, and micro-architecture development
- Experience communicating technical design decisions and trade-offs to cross-functional partners such as verification, physical design, and architecture teams Experience with one or more infrastructure IP areas, such as clock generation, distribution, and power management
- Exposure to subsystem-level implementation or integration, in any part of the flow from specification through RTL signoff
- Interest in growing into an infrastructure IP and subsystem implementation role
- Experience with microcontroller clusters
- Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)
- Experience adhering to and implementing responsible, ethical AI practices (e.g., risk assessment, bias mitigation, quality and accuracy reviews)
- Demonstrated ongoing AI skill development (e.g., prompt/context engineering, agent orchestration) and staying current with emerging AI technologies