DFT Engineer (RDSS Intern) - 2027

NVIDIA·Taipei City, Taiwan | Hsinchu, Hsinchu City, Taiwan·posted 5d ago · last seen just now

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About interviewing at NVIDIA

Recruiter screen, a technical screen mixing resume deep-dive with live coding, a hiring-manager conversation, then a panel of three to five 45–60 minute rounds: coding, systems design under hardware constraints, a domain deep-dive, and behavioral. Highly team-specific — you interview directly with the team — with C++ depth expected almost universally and decisions sometimes taking five-plus weeks after the panel.

Read the full NVIDIA interview process →

Description

By submitting your resume, you’re expressing interest in our 2027 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying the role.

NVIDIA is seeking phenomenal engineers to improve our verification methodology, so we can validate the world’s largest design efficiently. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

 

We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. We are now looking for a DFT Engineer in our Taiwan, Taipei/Hsinchu Office!

What you’ll be doing:

  • Verify our custom IP macros.

  • Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP level, cluster level, and full chip level

  • Collaborate with CAD team to optimize & smooth our simulation flow

  • Generating test patterns and perform silicon bring-up

What we need to see:

  • Master degree of Electrical Engineering/Computer Engineering/Computer Science

  • Strong debugging and analytical skills with RTL/Gate-level design tracing(Verdi) and verification simulation tool(VCS).

  • Familiarity with SOC basic architecture (clock, reset, power rail, IO pad, package)

  • Understanding of Design for Testing including Scan/ATPG/BIST/JTAG is a plus

  • Skills of Python/Perl/Tck/C/C++ is a plus

Ways to stand out from the crowd:

  • Fluent English communication is required

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