SoC Clocks Design Automation Engineer

NVIDIA·Tel Aviv-Yafo, Tel Aviv District, Israel | Yokne'am Illit, North District, Israel | Ra'anana, Center District, Israel·posted 28d ago · last seen 16m ago

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About interviewing at NVIDIA

Recruiter screen, a technical screen mixing resume deep-dive with live coding, a hiring-manager conversation, then a panel of three to five 45–60 minute rounds: coding, systems design under hardware constraints, a domain deep-dive, and behavioral. Highly team-specific — you interview directly with the team — with C++ depth expected almost universally and decisions sometimes taking five-plus weeks after the panel.

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Description

NVIDIA is looking for a dedicated SoC Clocks Design Automation Engineer to join our Networking Silicon team. In this role, you’ll focus on developing and supporting clock-related design flows and methodologies for SoC and networking chips, ensuring efficient and high-quality design implementation. You’ll also chip in to SoC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. Introduction

What you'll be doing:

  • Develop and maintain design automation and methodologies for SoC and networking clock flows.

  • Collaborate with design, STA, and project teams to ensure timely and high-quality design closure.

  • Develop and improve SoC top-level automation scripts and flows built upon existing infrastructure and tools.

  • Support SoC integration and construction flow activities across multiple projects.

  • Assist in timing, power, and noise analysis to ensure efficient performance.

What we need to see:

  • B.Sc. or M.Sc. in Electrical or Computer Engineering, or relevant professional experience.

  • At least 2 years of confirmed experience in SoC design, design automation, or methodology development.

  • Strong programming or scripting skills in at least one language (Python preferred; Perl, Tcl, or Make are advantages).

  • Understanding of physical design concepts including placement, routing, timing closure, and ECO implementation.

  • Familiarity with EDA tools for synthesis, place-and-route, and timing analysis (Synopsys or Cadence flows).

  • Strong analytical, problem-solving, and soft skills.

Way to stand out from the crowd:

  • Experience developing or maintaining SoC design or automation flows.

  • Knowledge of timing-related analysis (crosstalk, noise, delay).

  • Background in power or timing optimization techniques.

  • Collaborative attitude with the ability to work effectively across multi-functional teams.

  • Self-motivated and eager to learn while improving existing design flows.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

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