Mixed Signal Verification Engineer

Summary

Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple’s premier SOCs. This is a critical job within Apple's Hardware Technology organization, and we'd love to have you join us. You will own RNM/SystemVerilog behavioral modeling and verification of analog/RF blocks (regulators, bandgaps, data converters, LNA/PA, mixers, PLLs) inside a large SoC, including self-checking models, assertions for analog/digital specs, and AMS environment setup with analog designers

Description

In this role, you will own the modeling and verification of advanced analog/RF blocks residing within a large SoC.

Key Responsibilities

Development of RNM RF/Analog models in SystemVerilog. Develop models with self-checking techniques. Assess required model accuracy level depending on verification goals. Develop appropriate assertions to ensure analog/digital specs are respected and provide digital verification passing criteria. Work with Analog designers setting up AMS simulation environment. Debug complex chip digital-on-top testbenches and seek root causes for failures.

Minimum Qualifications

Minimum requirement of a bachelors degree. Strong fundamentals in analog/RF circuit theory/topologies. Experience with RNM coding in SystemVerilog.

Preferred Qualifications

MS and at least 3 years of industry experience is preferred Experience working with Cadence mixed signal verification environment. Ability to read analog schematics and extract related main functionality. Experience modeling mixed signal/RF blocks including biasing networks, power regulators, bandgaps, Opamp's, OTA's, data converters, LNA, PA, mixers, couplers, splitters, combiners, etc… Experience modeling high frequency PLL's is desired.