Physical Design Engineer

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Austin, Texas. Work with logic designer to decide on design hierarchy and to architect macro/design module placement to extract best PPA at floorplan stage. Work with EDA tools to optimize the design to get best placement location for millions of cells in the design. Construct clock tree to support high performance and low power designs. Route the design to meet all latest technology foundry guidelines and rules. Verify design performance using Static analysis, generate ECOs to fix failing paths. Verify design for electrical rules checks, design rule checks, electromigration and IR drop. Fix any of the violations on physical database. Review and signoff the design to make sure quality and PPA is not compromised. Identify issue, debug, resolve flow issues during place and route implementation. Develop scripts/programs as needed to implement designs. 40 hours/week.

Minimum Qualifications

Bachelor’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field. Experience and/or education must include: Using industry standard tools for PnR implementation Performing STA across multiple corners and modes, fixing setup/hold violations and debugging timing paths Creating a block-level floorplan including macro placement, pin assignment, power grid design, tap cell insertion, and congestion reduction. Running and debugging DRC/LVS using tools Fundamental understanding of clock trees including skew and insertion delays and impact on setup and hold timing Fundamental understanding of impact of drive strengths, vt-swapping and buffering on STA Implementing power (leakage recovery, Vt swaps) and functional changes (gate-level patching) Utilizing Tcl and Shell scripting to automate PnR flows, parse reports, or create CAD utilities

Preferred Qualifications

N/A