ASIC Engineer, Emulation

About

Meta is hiring ASIC engineers within the infrastructure organization. We are seeking a highly experienced Emulation Domain Expert to lead and drive advanced emulation model builds and flow for next-generation silicon products. As an ASIC Engineer in the Infra Silicon Enablement team, you will be part of a dynamic team working with experienced engineers across the industry, focused on developing and supporting innovative ASIC solutions for Meta’s data center applications.

Responsibilities

• Architect, develop, and optimize emulation model builds across Palladium, Protium, and Zebu platforms, supporting complex SoC and IP prototyping for data center and AI applications
• Lead methodology and flow development for hybrid emulation, accelerated verification, and co-simulation, integrating new tools and technologies into existing flows
• Drive continuous improvement in emulation flows, CI/CD automation, and infrastructure for scalable and reliable model release and qualification
• Collaborate with cross-functional teams (Design, DV, Validation, SW, Vendors) to deliver robust emulation environments and resolve technical challenges
• Own intake, validation, and deployment of third-party vendor capabilities, including feasibility evaluation, integration, and rollout
• Provide technical leadership and mentorship to team members, fostering growth and knowledge sharing
• Enable and debug high-speed interfaces (PCIe, USB, Ethernet) and networking protocols in emulation environments
• Support AI training and inference accelerator bring-up, validation, and performance optimization in emulation
• Proactively resolve build issues, blockers, and ensure high standards of model quality and reliability

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
• 2+ years of experience with hardware emulation, verification, prototyping, ASIC development cycles, pre/post silicon validation, emulation methodologies, hybrid flows, CI/CD automation, and infrastructure
• Experience in Verilog, SystemVerilog, Python, C/C++ and/or similar languages
• Experience working with internal and external partners for ASIC and/or system development
• Demonstrated ability to lead complex technical initiatives and mentor other engineers
• Experience solving complex technical problems and communicating decisions to technical and non-technical stakeholders across cross-functional teams Exposure to PCIe, USB, Ethernet, and networking domain protocols
• Familiarity with industry best practices for model building, release, and qualification
• Knowledge of processor designs, GPUs, and the debug subsystem is highly desirable
• Experience with emulation model builds and flows on Palladium, Protium, and Zebu platforms
• Exposure to networking SoCs and AI SoCs, including bring-up, validation, and performance optimization in emulation environments
• Experience in driving improvements for emulation efficiency, automation, and capacity planning
• Experience with AI training and inference accelerators, including bring-up and validation